1. Field of the Invention
This invention generally relates to analog-to-digital converters (ADCs) and, more particularly, to a system and method for converting voltage-to-time, and then time-to-digital information.
2. Description of the Related Art
One promising way of performing very high speed analog-to-digital (A-to-D) conversion in today's most advanced CMOS technologies is to utilize time domain analog signal processing. There, the A-to-D conversion process is split in two steps. In the first step the input voltage is converted into a time domain signal using pulse position or pulse width modulation. In the second step this signal is digitized using a time-to-digital converter (TDC). The advantage of this method is that most of the complexity of the design is in the TDC part, which can be implemented in digital, or digital like circuitry that enjoys all the benefits of technology scaling of the CMOS process. A well-known example of this type of ADC is the single-slope ADC, which uses a simple digital counter as TDC.
FIG. 1 is a simplified schematic of an ADC comprised of a voltage-to-time (V2T) converter and a TDC based upon a single slope principle (prior art).
FIG. 2 is a waveform illustrating the operation of voltage to time conversion over three clock cycles (prior art).
FIG. 3 is the signal transfer function from comparator input to comparator output in the circuit of FIG. 1 (prior art). In the first phase of a clock cycle the input voltage Vin is sampled into capacitor Cs through a switch, which is opened at the end of the phase. In the second phase the capacitor is discharged at a constant rate producing a voltage ramp as shown in FIGS. 2 and 3. A comparator is used to detect when the ramp reaches a predefine reference voltage level Vr. The length of the time interval (Td) from the start of the ramp (T0) until the moment the comparator fires is proportional to the voltage sampled into the capacitor. The ramp rate, which is determined by the capacitor size and the discharge current, defines the voltage to time conversion factor kVT. The duration of the ramp cannot exceed the period of the sampling, or in practice some fraction of it, as some time has to be reserved for sampling the input signal and transitioning between the phases. This restriction puts an upper limit on kVT for a given sampling rate.
The resolution, or dynamic range of an ADC is determined by the ratio of the largest allowable input signal and the smallest signal that can be detected. When the digitization occurs in the time domain, the smallest signal is equivalent to the least significant bit (LSB) of the TDC, which is ultimately limited by thermal noise, manifesting itself as jitter in the time domain. In addition to the noise, the LSB accuracy is affected by static and dynamic mismatch of the circuit elements. While in principle these effects can be measured and calibrated out, the smaller the LSB size, the more complex the calibration becomes. Further, lowering the noise usually comes at the cost of increased power consumption. For these reasons it is more attractive to increase the dynamic range by increasing the maximum input signal level than reducing the size of the LSB. In high speed applications the link between the maximum value of kVT and the V2T sampling rate sets the limit for maximum signal level in the time domain.
It would be advantageous if the dynamic range of an ADC could be increased without reducing the TDC LSB size.